To convert a std_logic_vector to an integer using "To_integer" if the code in vhdl using the library "IEEE.numeric_std.all," but when you do a project hdl not write this library by default instead can use the command conv_integer, located in the library "ieee.std_logic_arith.all" should not be used while the two libraries.I had this problem when trying to recreate a synchronous RAM, whose example is available on the slides
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To convert a std_logic_vector to an integer using "To_integer" if the code in vhdl using the library "IEEE.numeric_std.all," but when you do a project hdl not write this library by default instead can use the command conv_integer, located in the library "ieee.std_logic_arith.all" should not be used while the two libraries.I had this problem when trying to recreate a synchronous RAM, whose example is available on the slides
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