First project feedback

Hello guys..

In this web page http://sites.google.com/site/digitales1files/ you can find your report feedback. Please take note of the observations made in order to not doing again...

First project submision

Hello folks...

Just to remind you that the report submision deadline is next monday at 8:00 PM, delays will be not accepted. Also, you must submit all your .vhdl files, including simulation, into a single either .zip or .rar file.

Here it is the Report Model Unimag. I strongly recommend edit this file instead of doing a new one. There is no page limit but keep in mind the shorter, the better.

You should take into account the following guidelines for your report:

1. Avoid writing theorical content (assume that readers are familiar with digital systems) and focus on a detailed description of your project.
2. Figures and tables are very important for your report. Every single figure and table must be numered and commented in the text explaining every detailed of it. You should not include any VHDL code in your report, you should include block diagrams in order to explain your system. Results of your synthesis process must be showed in your report (you can see this doubling click on the Synthesize-XST bottom in the process window and then double click on View RTL Schematic). Your report must be full of simulation diagrams of your project.
3. Take into account I do not use Microsoft Office. Therefore, sending your report as .DOCX file is a BAD IDEA because although I can open this type of file some format can be lost. You can send the file as .doc file and the best idea is sending it as .pdf file.
4. Check this file as Reference of a good report example.

VHDL Netlist Slides

Exam problems

Hi guys

Check this combinatorial problems for you to practice...

Check the first term exam paper from last semester of Digitales 2 First Exam Paper 2009-2. You can ignore memory exercises (1, 2 and 3) and focus on 4 and 5.

Here you can check the first term exam paper from last semester Electiva 1 First Exam Paper 2009-2

Combinatorial VHDL Slides